1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a testing method for the semiconductor memory device.
2. Description of the Related Art
Conventionally, semiconductor memory devices are tested at a wafer level after being manufactured. When memory cells are identified as being of poor quality from the wafer level test, the memory cells are repaired. Then, the semiconductor memory devices pass through a packaging process to be tested at the package level, and semiconductor memory devices of good quality are the end product.
During the package level test, an interface distance for communication between the semiconductor testing equipment and the semiconductor memory device being tested is short. A high-frequency operation test is therefore possible. However, this is not the case during the wafer level test and thus a high-frequency clock signal for a high-frequency operation test is not properly provided. In addition, due to limitations of the testing equipment for the wafer level test, a high-frequency test cannot be performed at an actual operation frequency of the semiconductor memory device.
Therefore, from among various operation timing parameters of a semiconductor memory device, the wafer level test is performed only for limited parameters. Due to these limitations, defects may not be found in the wafer level test, and there is a possibility that defects not found in the wafer level test may also not be found during the package level test.